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 EMIF02-USB03F2
2-line IPADTM, EMI filter including ESD protection
Features

2-line low-pass-filter + 2-line ESD protection High efficiency in EMI filtering Lead-free package Very low PCB space occupation: < 3.25 mm2 Very thin package: 0.65 mm High efficiency in ESD suppression (IEC61000-4-2 level 4) High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging
ID Dz Pup
Flip Chip (11 bumps)
Figure 1.
Pin layout (bump side)
3 2 1 A
Pd1
Complies with the following standards
Vbus
IEC 61000-4-2 level 4 on external pins: - 15 kV (air discharge) - 8 kV (contact discharge) IEC 61000-4-2 level 1 on internal pins: - 2 kV (air discharge) - 2 kV (contact discharge)
B C D
D+ out Dout
Pd2
D+ in Din
GND
Figure 2.
Schematic
Pup Dz ID Vbus
Application
ESD protection and EMI filtering for:
D+OUT D-OUT
EMIF02-USB03F2
R3=1.3k R2=33 R1=33 C C R5=15k R4=17k
D+IN D-IN
USB OTG port
Description
The EMIF02-USB03F2 is a highly integrated array designed to suppress EMI / RFI noise for USB OTG (on-the-go). The EMIF02-USB03F2 Flip Chip packaging means the package size is equal to the die size. Additionally, this filter includes ESD protection circuitry which prevents damage to the protected device when subjected to ESD surges up to 15 kV on external contacts.
Pd2 Pd1
Cline = 20 pF max.
TM: IPAD is a trademark of STMicroelectronics.
April 2008
Rev 4
1/8
www.st.com 8
Characteristics
EMIF02-USB03F2
1
Characteristics
Table 1.
Symbol
Absolute ratings (Tamb = 25 C)
Parameter and test conditions Internal pins (D3, C3, C2, B2, B1): ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge External pins (D1, C1, A2, A3, B3): ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge Maximum junction temperature Operating temperature range Storage temperature range Value Unit
VPP
2 2 15 8 125 -40 to +85 -55 to 150
kV
Tj Top Tstg
C C C
Table 2.
Symbol VBR IRM VRM VCL Rd IPP Cline Symbol VBR IRM Cline R1, R2 R3 R4 R5
Electrical characteristics (Tamb = 25 C)
Parameters Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Input capacitance per line Test conditions IR = 1 mA VRM = 3 V @0V Tolerance 5 % Tolerance 5 % Tolerance 5 % Tolerance 5 % 33 1.30 17 15 Min 14 0.1 0.5 20 Typ Max Unit V A pF k k k
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EMIF02-USB03F2
Characteristics
Figure 3.
0.00 dB -10.00
Filtering measurement
EMIF02-USB03F2_EVAL-SAMPLES_PM431 Aplac 7.70 User: ST Microelectronics Jul 22 2004
Figure 4.
0.00 dB -10.00 -20.00 -30.00
Analog crosstalk measurement
EMIF02-USB03F2_EVAL-SAMPLES_PM431 Aplac 7.70 User: ST Microelectronics Jul 22 2004
-20.00
-40.00 -50.00
-30.00
-60.00 -70.00
-40.00
-80.00 -90.00
-50.00 100.0k 1.0M C1/C3 Line 10.0M f/Hz D1/D3 Line 100.0M 1.0G
-100.00 100.0k 1.0M C1/D3 Line 10.0M f/Hz 100.0M A2/A3 Line 1.0G
Figure 5.
ESD response to IEC 61000-4-2 (+15 kV air discharge) on one input V(in) and on one output V(out)
Figure 6.
ESD response to IEC 61000-4-2 (-15 kV air discharge) on one input V(in) and on one output V(out)
Figure 7.
Junction capacitance versus reverse voltage applied (typical values)
C(pF)
20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 11 12
V R (V)
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Application information
EMIF02-USB03F2
2
Application information
Figure 8. Application schematic
Vbus 3.3V ID Pup Dz ID Vbus
Vbus ID
USB OTG Xceiver
EMIF02-USB03F2
R3=1.3k
D+ D-
D+OUT D-OUT
C C
R2=33 R1=33
D+IN D+ D-IN D-
R5=15k
R4=17k
GND Pd2 Pd1
GND
R1 = R2 = 33 Cline = 20 pF max.
Figure 9.
Aplac model
C3 Ls Port1 50 A3 A2 B3 B2 B1 C2 D2 MODEL = D02_usb03_gnd MODEL = D02_usb03 bulk bulk B2 B1 R_1k3 C3 R_33R R_17k C1 D3 R_33R bulk bulk bulk bulk bulk C2 D2 R_15k D1 Lbump Rbump MODEL = D02_usb03 MODEL = D02_usb03 Cgnd Lgnd bulk Cbump Rsubump A2 Cbump Rsubump B2 Cbump Rsubump C2 Cbump Rsubump C3 Cbump Rsubump B3 bulk A3 bulk D1 Cbump Rsubump bulk bulk D3 Cbump Rsubump bulk bulk C1 Cbump Rsubump bulk bulk B1 Cbump Rsubump bulk bulk bulk Cbump Rsubump bulk bulk Rgnd Rs Lbump Rbump C1 Rbump Lbump Rs Ls Port2 50
Figure 10. Aplac parameters
Ls 950pH Rs 150m R_33R 33 R_1k3 1.3k R_15k 15k R_17k 17k Cz_usb03 11pF Rs_usb03 1 Cz_usb03_gnd 220pF Rs_usb03_gnd 0.9 Lgnd 50pH Rgnd 100m Cgnd 0.15pF Lbump 50pH Rbump 20m Cbump 2.4pF Rsubump 100m
4/8
USB OTG connector
EMIF02-USB03F2
Ordering information scheme
3
Ordering information scheme
Figure 11. Ordering information scheme
EMIF
EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip chip x = 2: lead free, pitch = 500 m, bump = 315 m
yy
-
xxx zz
Fx
4
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 12. Package dimensions
500 m 50 315 m 50 650 m 65
500 m 50
285 m
1.57 mm 50 m
285 m
2.07 mm 50 m
5/8
Ordering information
EMIF02-USB03F2
Figure 13. Footprint
Copper pad Diameter: 250 m recommended, 300 m max. Solder stencil opening: 330 m recommended
Figure 14. Marking
Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week)
E
Solder mask opening recommendation: 340 m min. for 300 m copper pad diameter
xxz y ww
Figure 15. Flip Chip tape and reel specification
Dot identifying Pin A1 location 4 0.1 O 1.5 0.1
1.75 0.1 3.5 0.1
2.17
0.73 0.05
All dimensions in mm
8 0.3
ST E
ST E
ST E
xxz yww
User direction of unreeling
xxz yww
xxz yww
4 0.1
1.67
Note:
More information is available in the application notes: AN1235:"Flip Chip: Package description and recommendations for use" AN1751: "EMI filters: Recommendations and measurements"
5
Ordering information
Table 3. Ordering information
Marking FU Package Flip Chip Weight 4.5 mg Base qty 5000 Delivery mode Tape and reel 7"
Order code EMIF02-USB03F2
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EMIF02-USB03F2
Revision history
6
Revision history
Table 4.
Date 14-Oct-2004 25-Oct-2004 27-Oct-2004 28-Apr-2008
Document revision history
Revision 1 2
3
Changes Initial release. Figure 14.: Flip Chip marking dimensions updated. Minor layout update. No content change. Updated ECOPACK statement. Updated Figure 11, Figure 12, Figure 13, Figure 14 and Figure 15. Reformatted to current standards.
4
7/8
EMIF02-USB03F2
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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
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